mirror of https://github.com/rust-lang/rust
45 lines
1.3 KiB
Rust
45 lines
1.3 KiB
Rust
//@ revisions: x86-avx512
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//@ [x86-avx512] compile-flags: --target=x86_64-unknown-linux-gnu -C llvm-args=-x86-asm-syntax=intel
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//@ [x86-avx512] compile-flags: -C target-feature=+avx512f,+avx512vl,+avx512bw,+avx512dq
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//@ [x86-avx512] needs-llvm-components: x86
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//@ [x86-avx512] min-llvm-version: 18.0
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//@ assembly-output: emit-asm
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//@ compile-flags: --crate-type=lib -O
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#![feature(no_core, lang_items, repr_simd, intrinsics)]
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#![no_core]
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#![allow(non_camel_case_types)]
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// Because we don't have core yet.
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#[lang = "sized"]
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pub trait Sized {}
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#[lang = "copy"]
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trait Copy {}
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#[repr(simd)]
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pub struct f64x4([f64; 4]);
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#[repr(simd)]
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pub struct m64x4([i64; 4]);
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#[repr(simd)]
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pub struct pf64x4([*const f64; 4]);
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extern "rust-intrinsic" {
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fn simd_gather<V, M, P>(values: V, mask: M, pointer: P) -> V;
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}
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// CHECK-LABEL: gather_f64x4
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#[no_mangle]
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pub unsafe extern "C" fn gather_f64x4(mask: m64x4, ptrs: pf64x4) -> f64x4 {
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// FIXME: This should also get checked to generate a gather instruction for avx2.
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// Currently llvm scalarizes this code, see https://github.com/llvm/llvm-project/issues/59789
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//
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// x86-avx512: vpsllq ymm0, ymm0, 63
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// x86-avx512-NEXT: vpmovq2m k1, ymm0
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// x86-avx512-NEXT: vpxor xmm0, xmm0, xmm0
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// x86-avx512-NEXT: vgatherqpd ymm0 {k1}, ymmword ptr [1*ymm1]
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simd_gather(f64x4([0_f64, 0_f64, 0_f64, 0_f64]), ptrs, mask)
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}
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