mirror of https://github.com/rust-lang/rust
164 lines
6.4 KiB
Rust
164 lines
6.4 KiB
Rust
//@ run-pass
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#![allow(non_camel_case_types)]
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//@ ignore-emscripten FIXME(#45351) hits an LLVM assert
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#![feature(repr_simd, intrinsics)]
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#[repr(simd)]
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#[derive(Copy, Clone)]
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struct i32x4(pub i32, pub i32, pub i32, pub i32);
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#[repr(simd)]
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#[derive(Copy, Clone)]
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struct U32<const N: usize>([u32; N]);
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#[repr(simd)]
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#[derive(Copy, Clone)]
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struct f32x4(pub f32, pub f32, pub f32, pub f32);
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macro_rules! all_eq {
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($a: expr, $b: expr) => {{
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let a = $a;
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let b = $b;
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assert!(a.0 == b.0 && a.1 == b.1 && a.2 == b.2 && a.3 == b.3);
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}};
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}
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macro_rules! all_eq_ {
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($a: expr, $b: expr) => {{
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let a = $a;
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let b = $b;
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assert!(a.0 == b.0);
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}};
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}
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extern "rust-intrinsic" {
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fn simd_add<T>(x: T, y: T) -> T;
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fn simd_sub<T>(x: T, y: T) -> T;
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fn simd_mul<T>(x: T, y: T) -> T;
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fn simd_div<T>(x: T, y: T) -> T;
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fn simd_rem<T>(x: T, y: T) -> T;
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fn simd_shl<T>(x: T, y: T) -> T;
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fn simd_shr<T>(x: T, y: T) -> T;
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fn simd_and<T>(x: T, y: T) -> T;
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fn simd_or<T>(x: T, y: T) -> T;
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fn simd_xor<T>(x: T, y: T) -> T;
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fn simd_neg<T>(x: T) -> T;
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fn simd_bswap<T>(x: T) -> T;
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fn simd_bitreverse<T>(x: T) -> T;
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fn simd_ctlz<T>(x: T) -> T;
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fn simd_ctpop<T>(x: T) -> T;
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fn simd_cttz<T>(x: T) -> T;
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}
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fn main() {
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let x1 = i32x4(1, 2, 3, 4);
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let y1 = U32::<4>([1, 2, 3, 4]);
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let z1 = f32x4(1.0, 2.0, 3.0, 4.0);
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let x2 = i32x4(2, 3, 4, 5);
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let y2 = U32::<4>([2, 3, 4, 5]);
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let z2 = f32x4(2.0, 3.0, 4.0, 5.0);
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let x3 = i32x4(0, i32::MAX, i32::MIN, -1_i32);
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let y3 = U32::<4>([0, i32::MAX as _, i32::MIN as _, -1_i32 as _]);
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unsafe {
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all_eq!(simd_add(x1, x2), i32x4(3, 5, 7, 9));
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all_eq!(simd_add(x2, x1), i32x4(3, 5, 7, 9));
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all_eq_!(simd_add(y1, y2), U32::<4>([3, 5, 7, 9]));
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all_eq_!(simd_add(y2, y1), U32::<4>([3, 5, 7, 9]));
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all_eq!(simd_add(z1, z2), f32x4(3.0, 5.0, 7.0, 9.0));
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all_eq!(simd_add(z2, z1), f32x4(3.0, 5.0, 7.0, 9.0));
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all_eq!(simd_mul(x1, x2), i32x4(2, 6, 12, 20));
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all_eq!(simd_mul(x2, x1), i32x4(2, 6, 12, 20));
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all_eq_!(simd_mul(y1, y2), U32::<4>([2, 6, 12, 20]));
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all_eq_!(simd_mul(y2, y1), U32::<4>([2, 6, 12, 20]));
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all_eq!(simd_mul(z1, z2), f32x4(2.0, 6.0, 12.0, 20.0));
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all_eq!(simd_mul(z2, z1), f32x4(2.0, 6.0, 12.0, 20.0));
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all_eq!(simd_sub(x2, x1), i32x4(1, 1, 1, 1));
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all_eq!(simd_sub(x1, x2), i32x4(-1, -1, -1, -1));
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all_eq_!(simd_sub(y2, y1), U32::<4>([1, 1, 1, 1]));
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all_eq_!(simd_sub(y1, y2), U32::<4>([!0, !0, !0, !0]));
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all_eq!(simd_sub(z2, z1), f32x4(1.0, 1.0, 1.0, 1.0));
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all_eq!(simd_sub(z1, z2), f32x4(-1.0, -1.0, -1.0, -1.0));
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all_eq!(simd_div(x1, x1), i32x4(1, 1, 1, 1));
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all_eq!(simd_div(i32x4(2, 4, 6, 8), i32x4(2, 2, 2, 2)), x1);
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all_eq_!(simd_div(y1, y1), U32::<4>([1, 1, 1, 1]));
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all_eq_!(simd_div(U32::<4>([2, 4, 6, 8]), U32::<4>([2, 2, 2, 2])), y1);
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all_eq!(simd_div(z1, z1), f32x4(1.0, 1.0, 1.0, 1.0));
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all_eq!(simd_div(z1, z2), f32x4(1.0 / 2.0, 2.0 / 3.0, 3.0 / 4.0, 4.0 / 5.0));
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all_eq!(simd_div(z2, z1), f32x4(2.0 / 1.0, 3.0 / 2.0, 4.0 / 3.0, 5.0 / 4.0));
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all_eq!(simd_rem(x1, x1), i32x4(0, 0, 0, 0));
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all_eq!(simd_rem(x2, x1), i32x4(0, 1, 1, 1));
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all_eq_!(simd_rem(y1, y1), U32::<4>([0, 0, 0, 0]));
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all_eq_!(simd_rem(y2, y1), U32::<4>([0, 1, 1, 1]));
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all_eq!(simd_rem(z1, z1), f32x4(0.0, 0.0, 0.0, 0.0));
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all_eq!(simd_rem(z1, z2), z1);
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all_eq!(simd_rem(z2, z1), f32x4(0.0, 1.0, 1.0, 1.0));
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all_eq!(simd_shl(x1, x2), i32x4(1 << 2, 2 << 3, 3 << 4, 4 << 5));
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all_eq!(simd_shl(x2, x1), i32x4(2 << 1, 3 << 2, 4 << 3, 5 << 4));
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all_eq_!(simd_shl(y1, y2), U32::<4>([1 << 2, 2 << 3, 3 << 4, 4 << 5]));
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all_eq_!(simd_shl(y2, y1), U32::<4>([2 << 1, 3 << 2, 4 << 3, 5 << 4]));
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// test right-shift by assuming left-shift is correct
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all_eq!(simd_shr(simd_shl(x1, x2), x2), x1);
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all_eq!(simd_shr(simd_shl(x2, x1), x1), x2);
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all_eq_!(simd_shr(simd_shl(y1, y2), y2), y1);
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all_eq_!(simd_shr(simd_shl(y2, y1), y1), y2);
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// ensure we get logical vs. arithmetic shifts correct
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let (a, b, c, d) = (-12, -123, -1234, -12345);
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all_eq!(simd_shr(i32x4(a, b, c, d), x1), i32x4(a >> 1, b >> 2, c >> 3, d >> 4));
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all_eq_!(
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simd_shr(U32::<4>([a as u32, b as u32, c as u32, d as u32]), y1),
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U32::<4>([(a as u32) >> 1, (b as u32) >> 2, (c as u32) >> 3, (d as u32) >> 4])
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);
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all_eq!(simd_and(x1, x2), i32x4(0, 2, 0, 4));
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all_eq!(simd_and(x2, x1), i32x4(0, 2, 0, 4));
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all_eq_!(simd_and(y1, y2), U32::<4>([0, 2, 0, 4]));
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all_eq_!(simd_and(y2, y1), U32::<4>([0, 2, 0, 4]));
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all_eq!(simd_or(x1, x2), i32x4(3, 3, 7, 5));
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all_eq!(simd_or(x2, x1), i32x4(3, 3, 7, 5));
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all_eq_!(simd_or(y1, y2), U32::<4>([3, 3, 7, 5]));
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all_eq_!(simd_or(y2, y1), U32::<4>([3, 3, 7, 5]));
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all_eq!(simd_xor(x1, x2), i32x4(3, 1, 7, 1));
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all_eq!(simd_xor(x2, x1), i32x4(3, 1, 7, 1));
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all_eq_!(simd_xor(y1, y2), U32::<4>([3, 1, 7, 1]));
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all_eq_!(simd_xor(y2, y1), U32::<4>([3, 1, 7, 1]));
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all_eq!(simd_neg(x1), i32x4(-1, -2, -3, -4));
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all_eq!(simd_neg(x2), i32x4(-2, -3, -4, -5));
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all_eq!(simd_neg(z1), f32x4(-1.0, -2.0, -3.0, -4.0));
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all_eq!(simd_neg(z2), f32x4(-2.0, -3.0, -4.0, -5.0));
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all_eq!(simd_bswap(x1), i32x4(0x01000000, 0x02000000, 0x03000000, 0x04000000));
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all_eq_!(simd_bswap(y1), U32::<4>([0x01000000, 0x02000000, 0x03000000, 0x04000000]));
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all_eq!(
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simd_bitreverse(x1),
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i32x4(0x80000000u32 as i32, 0x40000000, 0xc0000000u32 as i32, 0x20000000)
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);
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all_eq_!(simd_bitreverse(y1), U32::<4>([0x80000000, 0x40000000, 0xc0000000, 0x20000000]));
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all_eq!(simd_ctlz(x1), i32x4(31, 30, 30, 29));
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all_eq_!(simd_ctlz(y1), U32::<4>([31, 30, 30, 29]));
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all_eq!(simd_ctpop(x1), i32x4(1, 1, 2, 1));
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all_eq_!(simd_ctpop(y1), U32::<4>([1, 1, 2, 1]));
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all_eq!(simd_ctpop(x2), i32x4(1, 2, 1, 2));
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all_eq_!(simd_ctpop(y2), U32::<4>([1, 2, 1, 2]));
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all_eq!(simd_ctpop(x3), i32x4(0, 31, 1, 32));
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all_eq_!(simd_ctpop(y3), U32::<4>([0, 31, 1, 32]));
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all_eq!(simd_cttz(x1), i32x4(0, 1, 0, 2));
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all_eq_!(simd_cttz(y1), U32::<4>([0, 1, 0, 2]));
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}
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}
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